Field of the Invention
Embodiments of the present invention generally relate to integrated circuit chip packaging and, more specifically, to a package-on-package (POP) packaging system with a high power chip and a low power chip.
Description of the Related Art
With the development of the electronics industry, there are increasing demands for smaller electronic devices with improved performance. In order to achieve a higher integration density and a smaller footprint of electronic components, a so-called “package-on-package (POP)” technology has been developed. POP is a three-dimensional packaging technology used to vertically stack a plurality of leadframe-based semiconductor packages atop each other with an interface to route signals between them.
Minimizing the thickness of the package has been a challenge to the successful implementation of the POP technology since there is generally a trade-off between the thermal management of chips and other devices contained in the package and the performance of the devices. Specifically, by locating memory chips, passive devices, and other low-power components of an IC package as close as possible to the central processor unit (CPU) and other high-power devices in an IC package, communication between devices in the IC package is accelerated and packaging parasitics are reduced. However, heat generated by higher-power chips is known to adversely affect memory chips and other devices positioned nearby. Consequently, it is not thermally feasible to stack memory chips and passive devices directly on or under a CPU or other high-power chip when incorporated into a single IC package, since such a configuration necessarily limits the power of the high-power chip or affects the performance of the memory chips.
As the foregoing illustrates, there is a need in the art for a package system having a greater density of integrated circuits with a corresponding reduction in package size. More particularly, there is a need for a high-power chip and a low-power chip arrangement in a vertical stack which prevents heat transfer between the chips.